Nowadays, power semiconductor devices are necessary equipment in many different fields from small-sized electronic devices to automobiles, bullet trains, etc., and also to electric power transmission and distribution. The use areas and application fields have been increasing year by year, and in the fields of automobiles, bullet trains, electric power, and the like, higher current, higher breakdown voltage, and operation temperatures in a wide range, especially durability under high operation temperatures have been desired, not to mention high reliability and long lifetime. Since conventional solder-bonding techniques cannot ensure reliability of soldering materials under high temperatures, it is becoming more and more difficult to fabricate the elements that satisfy the conditions. As one of bonding techniques to solve this problem, the ultrasonic bonding has been introduced.
Here, a semiconductor device in which a conductive pattern is formed on a surface of an insulating substrate, and a semiconductor element and an electrode terminal are bonded to the conductive pattern is considered. Conventionally, the electrode terminal and the conductive pattern are subjected to the ultrasonic bonding at one position. When a power semiconductor element is used under conditions of high temperatures for a long period of time, a thermal stress is generated due to a difference in thermal expansion coefficients between the electrode terminal and the insulating substrate on which the conductive pattern is formed, and a bonding portion sometimes peels off.
In addition, as the semiconductor device carries larger current, it becomes necessary to increase a cross-sectional area of the electrode terminal. In other words, an increase in the thickness or the width of the electrode terminal requires an increase in the size of the electrode terminal. The increase in size of the electrode terminal causes an increase of the stiffness of the terminal. This results in an increase of a stress applied to the bonding portion accompanied by displacement of a package due to the heat generated by operation of the power semiconductor element, and thus a problem, such as reduction of bonding strength and terminal peeling, may occur.
Further, due to an increase in the thickness of the electrode terminal and the area of a bonding face, it becomes harder to propagate the energy of the ultrasonic bonding to the bonding face. To increase the bonding strength of the ultrasonic bonding, a bonding load and an ultrasonic output are generally increased as a countermeasure. However, the increase of these elements may cause a problem, i.e., the insulating substrate provided under the conductive pattern is damaged.
Accordingly, Patent Document 1 discloses a technique in which slits are provided at a plurality of positions between signal terminals that are subjected to the ultrasonic bonding, so that the ultrasonic bonding is stably performed. In addition, Patent Document 2 discloses a technique in which the ultrasonic bonding is performed at a plurality of positions between metal ribbons and electrode pads on a semiconductor chip to increase the area of the bonding face.